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Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

Cadence Accelerates Hyperscale SoC Design with Industry’s First Verification IP and System VIP for CXL 3.0

Next-generation CXL VIP and System VIP tools provide faster path to testing and compliance with the latest standard

Cadence Design Systems, Inc. announced the availability of the industry’s first Verification IP (VIP) and System-Level VIP (System VIP) for the Compute Express Link (CXL) 3.0 standard to accelerate the adoption of the new technology. The Cadence VIP for CXL 3.0 is integrated with the Cadence VIP for PCI Express (PCIe) 6.0, providing a complete solution from IP to the system-on-chip (SoC) level that helps users create designs for high-performance data center applications.

“CXL has become fundamental for hyperscale, data center, and cloud applications, and with the release of the CXL 3.0 specification, there is a need for tools that meet the latest requirements to ensure that early adopters can successfully build and verify their SoCs”

The Cadence VIP for CXL provides high-performance model implementation that allows designers to quickly and thoroughly complete functional verification with less effort and greater assurance that the design will operate as expected. The VIP for CXL features Cadence TripleCheck technology, which provides a specification-compliant verification plan linked to comprehensive coverage models and a robust test suite to ensure compliance with the specification.

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The Cadence System VIP solution has also been expanded to address the latest CXL specification. The solution includes the System Traffic Library for CXL that provides ready-to-use SoC-level tests that work seamlessly in both simulation and emulation, the System Performance Analyzer for automatic performance analysis from CXL to DDR, and the System Scoreboard that provides automatic coherency and data integrity checking.

“CXL is a disruptive technology that is quickly evolving, and early adopters need the ability to verify and ensure compliance with the specification to achieve the fastest path to IP verification closure,” said Jim Pappas, Director of Technology Initiatives, Intel Corporation. “We are delighted to see Cadence enabling advanced verification solutions for the newest standards, including the latest CXL 3.0 protocol.”

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CXL has become fundamental for hyperscale, data center, and cloud applications, and with the release of the CXL 3.0 specification, there is a need for tools that meet the latest requirements to ensure that early adopters can successfully build and verify their SoCs,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “The Cadence CXL VIP and System VIP are broad, highly differentiated, and industry-proven solutions. By supporting the industry’s newest specifications and providing first-to-market verification solutions for both IP and the SoC level, Cadence allows customers to quickly implement new standards, such as CXL 3.0.”

The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium® Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio and the vManager Verification Management Platform. The Cadence verification full flow delivers the highest verification throughput of bugs per dollar invested per day. The VIP solutions and verification full flow support the company’s Intelligent System Design strategy, enabling SoC design excellence.

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